Xbit-Labs reports that Intel’s future serverchipset ”Twin Castle” will be very different. The special with ”Twin Castle” is that the northbridge WONT contain a memory controller. ”Twin Castle” will consist out of three chip, the memory controller, the northbridge and the southbridge.

– Why has Intel chosen to ”remove” the memory controller from the northbridge? A northbridge to an Intel-mainboard contain two things, the  AGP- and memory-controller. The AGP-is very rarely updated, while the memory controller gets a an update now and then. The big advantage with ”removing” the memory controller from the northbridge is that it saves working hours. With the memory controller outside the northbridge Intel can really focus on developing the the memory controllerand doesn’t have to reinvent AGP 8x every time a new northbridge is created. By simply exchanging the memory controller you can have the same chipset with different types of memory support for example: XDR and DDR2.

Another advantage is that servermainboards will be able to have more memory controllers, which makes it possible for the processors to their own memory controller instead of sharing one. A server with dual Xeon-processors has today a shared memory controller of 533MHz (I.e. 266MHz for each). An Opteron-server on the other hand has memory controller per processor that is 333/400MHz which is of course a clear advantage for Opteron towards Xeon.

There is also another reason for ”Twin Castle” to have 3 chip, and that is that Intel want to use the same chipset for both Intanium and Xeon. Also to keep prices down. The only thing that you have to do with ”Twin Castle” to make it work with Intanium is a simple switsh of memory controller. This will gain above all gain Intanium which doesn’t sell as mcuh as Xeon.

Now that also the AGP-port willl be exchanged soon with PCI-Express the other part of the northbridge disappeares which bodes for singlechips solutions, which is much cheaper to develop and build mainboards around. This will might make future Pentium-mainboards consist out of centralbridge plus a memory controller, instead of the more classical north- and southbridge pair.

More info here.

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